1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and more particularly to improvement of a MOS input circuit.
2. Description of the Related Art
MOS circuits such as MOSIC or MOSLSI are frequently used, for example, as logic circuits each including a semiconductor memory, an inverter, etc. Each MOS circuit is formed by integrating MOSFETs each having an insulated gate electrode. However, such a MOS circuit is weak in insulation breakdown, and if a voltage, which is more than a rated voltage, is applied onto the MOS circuit, the MOS circuit is easily broken. In other words, if an overvoltage such as surge is applied onto an input terminal of the MOS circuit such as a CMOS circuit and a BiCOMS circuit and an overcurrent continues to flow, there is a case that a semiconductor device will be broken. Due to this, an overvoltage absorption element is generally provided at a signal input terminal.
In an input circuit portion of a conventional MOS integrated circuit, as shown in FIG. 1, an input node of an input gate circuit 51 such as a CMOS inverter circuit is connected to a signal input terminal 11 such as a bonding pad. Then, an overvoltage absorption element is connected to the input node. The overvoltage absorption element is structured such that a PMOS transistor 52 in which a gate and a source are mutually connected is connected between a power source voltage (Vcc) terminal and the signal input terminal 11, and an NMOS transistor 53 in which a gate and a source are mutually connected is connected between the signal input terminal 11 and a ground voltage (Vss) terminal.
In the input circuit portion, it is assumed that a forward voltage of a PN junction between a drain region and a substrate of the PMOS transistor 52 for over-voltage absorption is expressed by Vf. If a voltage whose level is higher than a voltage which is the sum of the forward voltage Vf and the power supply voltage Vcc (e.g., 5 V) is inputted to the signal input terminal 11, the input voltage, which is limited to (Vcc+Vf), is inputted to each gate of a PMOS transistor P1 and an NMOS transistor N1 of the CMOS inverter circuit 51. At this time, a potential difference between the gate and the source of the PMOS transistor P1 of the CMOS inverter circuit 51 is Vf. In contrast, the input voltage is directly applied between the gate and the source of the NMOS transistor N1 of the CMOS inverter circuit 51, and the potential difference between the source and the gate is (Vcc+Vf). Similarly, (Vcc+Vf) is applied between the drain and the gate of the overvoltage absorption element 53.
By the way, for example, a burn-in test, which is performed in a product qualification test of IC or a screening test in a manufacturing process thereof, is an acceleration test in which voltage stress and thermal stress are simultaneously added so as to assure thermal breakdown of a junction of the MOS transistor. On the other hand, it is difficult to assure long-time reliability between the source and the gate or between the drain and the gate by the present voltage/thermal acceleration test wherein a high voltage, which is more than a rated voltage, is applied onto a gate oxide film of the MOS transistor.
The breakdown of the gate oxide film depends on a gate material of the MOS transistor such as polycrystalline silicon and an electrical charge amount of a gate channel portion. A portion where the electrical charge is concentrated differs depending on the position on the same semiconductor wafer and its tendency is unclear. Therefore, it is extremely difficult to take measures against the concentration of the electrical charge in the manufacturing process. Due to this, there has been desired means for assuring reliability when the high voltage, which is higher than the rated voltage, is applied onto the gate oxide film for a long period time.